An analog multiplexer is applied to such a use in which a predetermined analog input is selected for an input of an analog to digital converter from a plurality of analog inputs. A conventional analog multiplexer comprises (n+1) input terminals to which (n+1) analog inputs are supplied respectively, an output terminal from which a selected analog output is supplied to a following stage, and (n+1) MOS FET circuits each passing and stopping a corresponding analog input dependent on a selection signal applied thereto. Each of the (n+1) MOS FET circuits is composed of an n-channel MOS FET and a p-channel MOS FET which are connected to face each other wherein the selection signal is applied to a gate electrode of the n-channel MOS FET, while an inverted signal of the selection signal is applied to a gate electrode of the p-channel MOS FET. In the above, n is a positive integer (n=1, 2, 3 . . . ).
In operation, the (n+1) analog inputs are supplied to the (n+1) input terminals, and the selection signal applied to one of the (n+1) MOS FET circuits becomes "1", while the remaining selection signals applied to the remaining MOS FET circuits of n become "0". As a result, the n and p-channel MOS FETs are turned on in the MOS FET circuit to which the selection signal "1" is applied, so that an analog input supplied to a corresponding input terminal is passed through the selected MOS FET circuit to be transmitted to the output terminal, while the n and p-channel MOS FETs are turned off in the non-selected MOS FET circuits of (n+1) to which the selection signals "0" are applied, so that analog inputs of n supplied to the remaining input terminals of n are not transmitted to the output terminal. Thus, a predetermined analog input signal is selected from the (n+1) analog input signals.
In the conventional analog multiplexer, however, there is a disadvantage that an analog output is changed even in a change of non-selected analog inputs because the output terminal is slightly connected to non-selected input terminals due to parasitic capacitances between source and drain electrodes etc. of the MOS FET circuits.